The present invention relates to a semiconductor memory, and more particularly to a technique for repairing a semiconductor memory in such a manner that defective memory cells are replaced by spare memory cells.
In recent years, the level of integration of a semiconductor memory has been increased at high speed, and a semiconductor memory having a storage capacity of 1 mega bits has been mass-produced. However, as the level of integration of a semiconductor memory is made larger, each element is decreased in size, and the semiconductor chip is increased in area. Thus, there arises a problem that the manufacturing yields of the memory become correspondingly reduced. In order to solve the problem, the so-called redundancy technique is used, in which defective memory cells are replaced by spare memory cells already provided on a chip. As discussed on pages 479 to 487 of the IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 5, October, 1981, the above technique is very effective for improving the manufacturing yields of a semiconductor memory.
In addition to the above technique, a redundancy method is proposed in JP-A-60-130,139, in which method a regular line in one of a plurality of memory mats can be replaced by a spare line in another memory mat. In this method, however, there arises the following problem. That is, in a case where a semiconductor memory is divided into a large number of memory mats, a complicated control operation is required to specify one of the memory mats. This is because a predetermined or another memory mat has to be selected in accordance with whether or not an address to be accessed is defective. Specifically in a case where a memory mat other than the predetermined memory mat is selected in a DRAM, it is required to operate a sense amplifier other than a predetermined sense amplifier. Thus, the access time associated with operation of the memory is increased.
FIG. 1A shows an example of a semiconductor memory which utilizes the redundancy technique and has been studied by the present inventors. In FIG. 1A, reference numeral 10 designates a memory array, in which memory cells are arranged so as to form a matrix. The memory array 10 is divided into a region 11 where regular memory cells are arranged, and a region 12 where spare memory cells are arranged. In the region 11, NWxc3x97NB memory cells are disposed at desired ones of two-level crossings of NW word lines W[i] (where i=0, 1, . . . NWxe2x88x921) and NB bit lines B[j] (where j=0, 1, . . . NBxe2x88x921). In the region 12, Lxc3x97NB memory cells (in the figure, L=4) are disposed at two-level crossings of L spare word lines SW[k] (where k=0, 1, . . . Lxe2x88x921) and the NB bit lines. In a case where a folded bit line structure is used, each bit line is formed of two wiring conductors, but only one wiring conductor is shown in the figure for the sake of simplicity. Further, in FIG. 1A, reference numeral 20 designates sense amplifiers for amplifying the signals read out from memory cells and input/output lines for transferring data (or common signal lines in a case where only input or output data is sent), 30 an X-decoder applied with row address signals AX[i] (where i=0, 1, . . . nwxe2x88x921, and nw=log2NW) for selecting one of NW word lines, 40 a Y-decoder applied with column address signals AY[j] (where j=0, 1, . . . nBxe2x88x921, and nB=log2NB) for selecting one of NB bit lines, 50 a redundancy control circuit, 60 a spare word line selection circuit applied with the output of the redundancy control circuit for selecting a spare word line, 701 a data input buffer, and 702 a data output buffer.
The present memory is provided with the redundancy control circuit for word lines. Accordingly, in a case where a regular word line is defective, the memory can be repaired in such a manner that the defective word line is replaced by one of the spare word lines with the aid of the redundancy control circuit 50 and the spare word line selection circuit 60. Further, L address comparing circuits AC[k] (where k=0, 1, . . . Lxe2x88x921) are provided on a one-to-one basis for each spare word line. Each address comparing circuit stores therein the row address of a defective word line, and checks whether or not an address to be accessed is coincident with the stored address. When the address to be accessed is coincident with the stored address, the output XR[k] of the address comparing circuit AC[k] used is set at a high level. The spare word line selection circuit 60, as shown in FIG. 1B, includes L spare word drivers 650. Each of the spare word drivers 650 is activated when the output XR[k] of a corresponding address comparing circuit AC[k] has a high level. Thus, a corresponding spare word line SW[k] is selected in response to a word line drive signal xcfx86X and the output of an NOR gate 501 is set at a low level thereby disabling the X-decoder 30. Accordingly, a regular word line which is to be selected, is never selected. That is, the regular word line is replaced by the spare word line SW[k].
FIG. 2A shows another example of a semiconductor memory which utilizes the redundancy technique and has been studied by the present inventors. In FIG. 2A, reference numeral 10 designates a memory array, in which memory cells are arranged so as to form a matrix. The memory array 10 is divided into a region 14 where regular memory cells are arranged, and a region 15 where spare memory cells are arranged. In the region 14, NWxc3x97NB memory cells are disposed at two-level crossings of NW word lines W[i] (where i=0, 1, . . . NWxe2x88x921) and NB bit lines B[j] (where j=0, 1, . . . NBxe2x88x921). In the region 15, Lxc3x97NW memory cells (in the figure, L=4) are disposed at two-level crossings of L spare bit lines SB[k] (where k=0, 1, . . . Lxe2x88x921) and the NW word lines. Further, in FIG. 2A, reference numeral 20 designates sense amplifiers for amplifying the signals read out from memory cells and input/output lines for transferring data, 30 an X-decoder applied with row address signals AX[i] (where i=0, 1, . . . nWxe2x88x921, and nW=log2NW) for selecting one of NW word lines, 40 a Y-decoder applied with column address signals AY[j] (where j=0, 1, . . . nBxe2x88x921, and nB=log2NB) for selecting one of NB bit lines, 50 a redundancy control circuit, and 63 a spare bit line selection circuit applied with the output of the redundancy control circuit for selecting a spare bit line.
The present memory is provided with the redundancy control circuit for bit lines. Accordingly, in a case where a regular bit line is defective, the memory can be repaired in such a manner that the defective bit line is replaced by one of the spare bit lines with the aid of the redundancy control circuit 50 and the spare bit line selection circuit 63. Further, L address comparing circuits AC[k] (where k=0, 1, . . . Lxe2x88x921) are provided on a one-to-one basis for each of L spare bit lines. Each address comparing circuit stores therein the column address of a defective bit line, and checks whether or not an address to be accessed is coincident with the stored address. When the address to be accessed is coincident with the stored address, the output YR[k] of the address comparing circuit AC[k] used is set at a high level. The spare bit line selection circuit 63, as shown in FIG. 2B, includes L drivers 680. Each of the drivers 680 is activated when the output YR[k] of a corresponding address comparing circuit AC[k] has the high level. Thus, a corresponding spare bit line SB[k] is connected to input/output lines I/O through MOS transistors 690 and 691, in response to a bit line selection signal xcfx86Y and the output of a NOR gate 501 is set at a low level thereby disabling the Y-decoder 40. Accordingly, a regular bit line which is to be selected, is never selected. That is, the regular bit line is replaced by the spare bit line SB[k].
The present inventors have studied the above-mentioned redundancy technique and have found that the following problem occurs when increasing the level of integration of a semiconductor memory. That is, when the level of integration of a semiconductor memory is increased, a large number of memory cells are simultaneously replaced by spare memory cells through the redundancy technique, and thus a probability that a defective spare memory cell is used, is increased. This is because a large number of memory cells are arranged along a single word or bit line. For example, in a 256 Kbit memory (NW=NB=512), 512 memory cells are simultaneously replaced by spare memory cells. While, in a 16 Mbit memory (NW=NB=4,096), 4,096 memory cells are simultaneously replaced by spare memory cells. When at least one of the spare memory cells substituted for regular memory cells is defective, a chip having the spare and regular memory cells is faulty. The redundancy technique is used on the premise that spare memory cells are not defective. Accordingly, when the level or degree of integration of a semiconductor memory is increased, the manufacturing yields thereof cannot be improved by the redundancy technique.
In a case where a large-scale semiconductor memory is constructed in such a manner that a memory array is divided into a plurality of memory mats, the above problem becomes even more serious. When a semiconductor memory is made large in scale, the number of memory cells connected to a single word (or bit) line is increased, and wiring length is increased. Thus, the parasitic resistance and capacitance of a wiring conductor are increased. Hence, there arises a problem that a signal propagation time is increased and a signal-to-noise ratio is reduced. In order to solve this problem, a practice widely employed is to divide a memory array into a plurality of memory mats, thereby shortening the wiring length of a single word (or bit) line. However, when the redundancy technique is applied to a semiconductor memory which is divided into memory mats, the following problem is further aroused.
FIG. 3 shows an example of a semiconductor memory which corresponds to a case where the memory array of FIG. 1A is divided into four memory mats (that is, each word line is divided into two parts, and each bit line is divided into two parts). In FIG. 3, reference numerals 100 to 103 designate memory mats, 200 to 203 sense amplifiers and input/output lines, 300 and 301 X-decoders, 400 a Y-decoder, 610 and 611 spare word line selection circuits, 700 a multiplexer, 701 a data input buffer, and 702 an data output buffer. Each memory mat includes a region 110, 111, 112, or 113 where regular memory cells are arranged, and a region 120, 121, 122, or 123 where spare memory cells are arranged. In each of the regions 110, 111, 112 and 113 (which correspond to the sub-regions 11A, 11B, 11C and 11D of FIG. 1A, respectively), NWxc3x97NB/4 memory cells are disposed at two-level crossings of NW/2 word lines and NB/2 bit lines. In each of the regions 120, 121, 122 and 123, Lxc3x97NB/2 memory cells (in the figure, L=4) are disposed at two-level crossings of L spare word lines and the NB/2 bit lines. For example, in a semiconductor memory described in the above-mentioned reference, NW/2=64, NB/2=128, and L=4.
Explanation will first be made of a word-line selecting method in the example of FIG. 3. In the present example, word lines are selected from a pair of memory mats. For example, at the same time as a word line W[i, 0] in the memory mat 110 is selected, a corresponding word line W[i, 2] in the memory mat 112 is selected. At this time, no word line in the memory mats 111 and 113 is selected. Similarly, when word lines in the memory mats 111 and 113 are selected, no word line in the memory mats 110 and 112 is selected. This is because the word lines W[i, 0] and W[i, 2] are made by dividing a single word line into two parts, and hence can be logically regarded as a single word line. Such is determined by one of the row address signals (in the present example, the address signal AX[nWxe2x88x921] indicative of the leftmost bit of a row address) as to which of a memory mat group 110 and 112 and a memory mat group 111 and 113 is to be selected. A memory cell is finally selected by using column address signals AY[j] (where j=0, 1, . . . nBxe2x88x921). At this time, the multiplexer 700 determines which of a memory cell in the memory mat 110 or 111 and a memory cell in the memory mat 112 or 113 is to be selected, by using one of the column address signals (in this example, the address signal AY[nBxe2x88x921] indicative of the leftmost bit of a column address).
In the present example, each address comparing circuit compares the row address signals other than the address signal AX[nWxe2x88x921] indicative of the leftmost bit, with the corresponding row address signals stored in the address comparing circuit. The outputs XR[k] of the address comparing circuits AC[k] are supplied to the spare word line selection circuit. The spare word line selection circuit, as shown in FIG. 4, makes the logical product of the row address signal AX[nWxe2x88x921] (or the complement thereof) and each of the outputs XR[k], to drive only a spare word line in the selected memory mat.
In the present memory, the replacement of a regular line by a spare line is made in all the memory mats at the same time. This fact will be explained below with reference to FIG. 5. FIG. 5 shows an example of a method of replacing word lines by spare word lines. In FIG. 5, defective word lines W[0, 0], W[2, 0], W[1, 1] and W[3, 3] are replaced by spare word lines SW[0, 0], SW[1, 0], SW[2, 1] and SW[3, 3], respectively. However, when the above replacement is carried out, other word lines are replaced by spare word lines. For example, at the same time as the defective word line W[0, 0] is replaced by the spare word line SW[0, 0], corresponding word lines W[0, 1], W[0, 2] and W[0, 3] in the memory mats 101, 102 and 103 are replaced by spare word lines SW[0, 1], SW[0, 2] and SW[0, 3], respectively.
In the example of FIG. 3, there arises the following problems. The first problem is that, as is apparent from the comparison of FIG. 3 with FIG. 1A, an area necessary for spare word lines is increased by dividing a memory array into memory mats. This is because each memory mat includes L spare word lines. A sub-region 12A shown in FIG. 1A corresponds to the regions 120 and 121 of FIG. 3, and a sub-region 12B shown in FIG. 1A corresponds to the regions 122 and 123 of FIG. 3. Hence, in the present example, an area for spare word lines is twice as large as that in the example of FIG. 1A. When each word line is divided into MW parts and each bit line is divided into MB parts, an area for spare word lines is generally increased by a factor of MB, and an area for spare bit lines is generally increased by a factor of MW, though the spare bit lines are not shown in FIGS. 1A and 3. Thus, a chip area is increased.
The second problem is that when a defective word line is replaced by a spare word line, a large number of memory cells are replaced by spare memory cells. This is because, as mentioned above, the replacement of a word line by a spare word line is made in all the memory mats at the same time. When each word line is divided into MW parts and each bit line is divided into MB parts, the number of spare memory cells which are simultaneously substituted for regular memory cells at a time a defective word line is replaced by a spare word line, is generally increased by a factor of MB, and the number of spare memory cells which are simultaneously substituted for regular memory cells at a time a defective bit line is replaced by a spare bit line, is generally increased by a factor of MW. As has been already mentioned, an increase in the number of spare memory cells simultaneously substituted for regular memory cells reduces the manufacturing yields. The first and second problems become serious in a large-scale integration memory, in which each of MW and MB has a large value.
FIG. 6 shows another method of applying the redundancy technique to a semiconductor memory, in which a memory array is divided into a plurality of memory mats. In FIG. 6, address comparing circuits are provided on a one-to-one basis for each of the spare word lines in the memory mats. Accordingly, 4L address comparing circuits (in the figure, eight address comparing circuits) are used. Each address comparing circuit compares row address signals AX[0] to AX[nWxe2x88x921] and column address signal Ay[nBxe2x88x921] indicative of the leftmost bit, with those stored in the circuit.
FIG. 7 shows how defective word lines are replaced by spare word lines, by way of example. As is apparent from the comparison of FIG. 7 with FIG. 5, the method shown in FIG. 6 is superior in two points to the method shown in FIG. 3. The first point is that the utilization efficiency of a spare word line is high, and thus the same number of defective word lines as in the example of FIG. 3 can be replaced by spare word lines even when the number of spare word lines per one memory mat is made smaller than that in the example of FIG. 3. This is because the probability that many defective word lines are included in one memory mat, is very low. The second point is that the number of spare memory cells which are simultaneously substituted for regular memory cells is small.
In the method shown in FIG. 6, however, there arises a problem that the number of address comparing circuits is increased. When each word line is divided into MW parts and each bit line is divided into MB parts, MWMBL address comparing circuits are generally required, and thus a chip area is increased. This problem is very serious in a large-scale integration memory, in which each of MW and MB has a large value.
According to the present invention, when a memory array is divided into M memory mats (where Mxe2x89xa72), the number m of word or bit lines which are simultaneously replaced by spare lines in accordance with the redundancy technique, is made smaller than the number M and equal to a divisor of the number M.
Further, an address comparing circuit can store therein not only logical values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d but also a don""t-care value xe2x80x9cXxe2x80x9d. When input data is compared with the don""t-care value, the result of comparison indicates xe2x80x9ccoincidencexe2x80x9d, independently of which of the logical values xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is indicated by the input data. FIG. 8 shows the results of comparison made by the address comparing circuit.
By making the number m smaller than the number M, the number of memory cells which are simultaneously replaced by spare memory cells, is decreased. Thus, the probability that the spare word lines are defective, is reduced. Accordingly, a redundancy control circuit capable of greatly improving the manufacturing yields can be formed even in a large-scale integration memory.
When the address comparing circuit is so constructed as to be capable of storing the don""t-care value xe2x80x9cXxe2x80x9d, each bit of an applied address can be selectively compared with a stored value. As shown in FIG. 8, when a logical value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is stored in the address comparing circuit, the result of comparison indicates xe2x80x9ccoincidentxe2x80x9d or xe2x80x9cnot coincidentxe2x80x9d in accordance with input data. That is, the stored value is compared with a corresponding bit of an input address. When the don""t-care value xe2x80x9cXxe2x80x9d is stored in the address comparing circuit, the result of comparison indicates xe2x80x9ccoincidentxe2x80x9d, independently of input data. That is, that bit of an input address which corresponds to the stored value, is not compared therewith. Thus, for example, the following defect-repairing operations can be performed.
When all the bits of an address (that is, all the bits of row and column addresses) are compared with stored values, each of regular memory cells can be replaced by a spare memory cell. When only a column address is compared with a stored column address, each bit line can be replaced by a spare bit line. When bits of a column address other than the rightmost bit are compared with stored values, a pair of memory cells can be replaced by a pair of spare memory cells. That is, various defects in a semiconductor memory such as a single-bit defect, a bit-line defect and a pair-bit defect, can be repaired. Thus, the manufacturing yields of a semiconductor memory can be made higher than that due to the conventional redundancy technique.
It is an object of the present invention to provide a redundancy technique which can greatly improve the manufacturing yields of a semiconductor memory without requiring a large chip area.
It is another object of the present invention to provide a redundancy technique which can enhance the utilization efficiency of spare bits.